7-2 Frequency Change and WDT The SH-3 and SH3-DSP CPU clock and peripheral clock can be changed using the frequency control register. However, when the change is like this, CPU operations must be stopped in the standby state until the frequency stabilizes. It is stopped by writing to the frequency control register, and it is released from standby by WDT overflow. For that reason the time to overflow in WDT is set to the standard 100µs or greater in the wait state. WDT also has the function to detect system hangup. For that reason register access is also restricted. Writes are always in word size, and access permission is set in the top portion.