6-4 Exception Handling Program of MMU These are MMU exception requests. A TLB miss (MMU page exception request) shows that translation information for a designated page is not registered in TLB. This exception request only is executed from the address 0×400. The program performs registration to TLB. The logical address is registered in the page table entry high (PTEH) register. The program checks it and writes the corresponding physical address to the page table entry low (PTEL) register. At this time, the page information is also set. Page size, access protection, cache subject and cache mode are specified. If the information is registered, the LDTLB instruction is executed to register it to TLB. The way can be specified in the MMUCR setting but usually it does not need to be specified as it is updated by a pseudo-LRU algorithm. Return is executed after TLB is set. At this time, the LDTLB instruction and RTE instruction should be separated by at least 2 instructions. This is an example of executing a program with address translation set up like this. This shows an example of a program. This function reads the setting value from this array (ptel[]) to the page table entry low register. It refers to the page number of the page table entry high register to determine which element to use. For other exception requests related to MMU, the exception handler is started from address 0×100. This table shows processing of exception handling and programs. These are examples of programs. This function (invTLB()) invalidates TLB. Entry is set as valid. This function (fstWrite()) processes the initial page write. The dirty bit is set to 1.