5-5 Prefetch The SuperH processors have buses connecting to the CPU and cache and bus state controller. These buses operate independently. While there are instruction or data access hits on the cache, the external bus is idle. If a program or data that has never been executed accesses the cache, it results in a miss, and the necessary information is filled to the cache from the external memory. Cache fill operation is executed from the cache miss information, but for SDRAM time for at least 3 bus clock cycles must pass before the operation can begin. During that time the CPU is idling. If this idling time is too long, it will degrade the overall performance of the system. CPU idling time can be reduced by reading information in advance while the external bus is idle during cache hits. That is called prefetch. SuperH processors provide instructions for prefetch. These are examples of using prefetch instructions. This function sets the external bus to idle state when there is a cache hit. It prefetches the top data in an array during that time. The top 4 data items can be prefetched from this array when it is mapped with 16 byte boundaries. Cache lock Use the cache lock function to prevent instructions or data filled in the cache from being overwritten, so it will always be a cache hit. SH7709S has a cache lock enable bit in the status register, which is set to 1. Specify the load way and execute the PREF instruction in cache control register 2. When the necessary load is completed, it locks like this. The program locks way 2.