| 2-6 Instructions and Address Mode |   |
| |
Instructions are made up of 2 operands.
They are written in assembly language as shown in the figure.
We’ll describe addressing modes and expressions of designations that can be specified with instruction operands.
It is called register direct mode when handling the content of internal registers of the CPU.
Most instructions in operations of the 2 operands are in register direct mode.
All address specifications during memory access are indirect. 16-bit instructions cannot collect 32-bit address information.
This is the addressing mode used when sending data.
Immediate mode uses 8 bit data.
We’ll describe instruction operations.
The table shows basic instructions for SH-1, improved and additional instructions for SH-2 and additional instructions for SH-3.
Data transfer with a general register is done with MOV instruction and available arithmetic operations are four operations and multiply/accumulate operations. Loop control is also available in SH-2 and later. In addition 32-bit multiplication and multiply/accumulate operations has been added so results can be obtained in 64 bits in SH-2 and later.
Logical operations use GBR so memory is operated directly.
There is also the TAS instruction that can be used as semaphore between multiprocessors.
The shift instruction has dynamic shift using a barrel shifter for arithmetical and logical operations.
When the top character in a branch instruction is B it is relative branching, and it is absolute branching when the character is J.
A position independent program can be created by using B as the top character for all branch instructions.
System control instructions are for access to the system registers and control registers. They include instructions that cannot be executed unless in privileged mode.
There are no dedicated instructions to operate cache.
The LDTLB instructions set MMU.