| 2-5 Control Registers |   |
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Status Register (SR)
This indicates the mode and current status of the CPU.
At reset, it is initialized into privileged mode, with the general register bank set to 1, exception requests blocked and the interrupt mask set to 15.
The operational status is indicated by the T bit only. Conditional branch instructions are also controlled by this T bit.
There are 4 interrupt mask bits, and masking can be controlled with the priority levels of 1 to 15, from low to high priorities.
The saturation S bit is used to suppress overflow from addition in multiply and accumulate operations.
M and Q are used for division. These bits automatically change during operations. The programmer doesn't have to set these bits manually.
It is possible in privileged mode only to execute instructions that change the SR.
Global Base Register (GBR)
This is used as the base address in the GBR indirect addressing mode.
When a member of an array or structure is accessed, the array or structure name is used as the pointer, and the target member is located by the relative distance from there. In that case, when 2 general registers are used for the pointer function and data, the instruction code allocates only 4bits to express the relative distance that can specify only 16 areas. The dedicated base register GBR is prepared to address this problem. It allows relative distance to be expressed in 8 bits so that it can handle 256 data items.
In addition using these 8 bits in immediate mode makes it possible to lock the bus and perform a logical operation on the memory contents without accepting any interrupt requests to obtain the result in the memory. GBR can be used for bit-by-bit logical operations on memory contents, such as the peripheral function registers.
Vector Base Register (VBR)
This indicates the base address for exception handling.
At reset it is initialized to H’00000000. It is effective when general purpose OSes that require the exception handler to be rewritten are used because it can allocate the exception handler from ROM at activation after reset and in RAM after activation.
Save Program Counter (SPC) and Save Status Register (SSR)
When a general exception request or interrupt request is accepted, these registers save the Program Counter (PC) and Status Register (SR).
The RTE instruction restores the PC and SR.
SPC and SSR for saving are one set. It should be programmed to carry out SPC/SSR save and restore operations in order to accept multiple exception requests.
PR is used to call subroutine procedures and SPC and SSR are used for handling exceptions such as accepting interrupt requests. The hardware does not require a stack area. However, C compilers require a stack area for nesting functions or local variables. Renesas uses R15 as the stack pointer in its C compiler.