1-6 Outline of SH3 and SH3-DSP Here is an overview of the SH-3 and SH3-DSP. We’ll pick up the SH7709S as an example of the SH-3. The maximum operating frequency of the CPU core, MMU and cache is 200MHz. The maximum operating frequency of the external bus interface is 66.67MHz. The DMA controller uses the bus state controller. The maximum operating frequency of these on-chip peripheral functions is 33.34MHz. It is possible to change the operating frequency of the CPU and on-chip peripheral functions except the bus state controller by the program. The device goes through standby when the oscillator circuit operation is changed and should be restored using the watchdog timer. It has the H-UDI debug function. It can use J-TAG emulators such as E10A. In addition it can use the AUD function for collecting data during emulation.